1. Field of the Invention
The present invention is related to a method of operating a PSRAM and related memory device, and more particularly, to a method of automatically adjusting latency of a PSRAM and related memory device.
2. Description of the Prior Art
Random access memory is a data storage device categorized into two types: static random access memory (SRAM) and dynamic random access memory (DRAM). In DRAM, each memory cell includes a transistor and a capacitor. The capacitor may either be charged or discharged. The transistor may function as a switch which allows a peripheral control circuit to access or change the status of the capacitor. Due to capacitor charge leakage, DRAM is required to periodically execute refresh operation in order to maintain accurate data. In SRAM, each memory cell includes bistable latching circuitry capable of storing date without executing refresh operation when powered. SRAM has faster data access, but occupies larger space and consumes more power.
Pseudo-static random access memory (PSRAM) adopts the memory cell structure of DRAM and the timing control of SRAM. It combines the high density of DRAM with the ease of use of SRAM. PSRAM offers variable latency with which the wait time for accessing a specific column address may be adjusted. The unit of latency is the period of the central clock signal. A larger latency means slower data access. When receiving an external command, a PSRAM may be executing a specific operation or has completed the specific operation but before meeting corresponding timing parameters. Under such circumstance, the PSRAM whose latency is set to one clock period can provide faster data access, but may not be able to access data accurately; the PSRAM whose latency is set to two clock periods is given sufficient time to complete the specific operation and meet corresponding timing parameters, but the overall data access speed is compromised.